1. Technical Field
This disclosure relates generally to abnormal connection detecting circuits for detecting abnormal connections between loads and output terminals, which circuits are provided in driving devices that supply currents to the loads. More particularly, the disclosure relates to an abnormal connection detecting circuit for detecting an open status in which a load is not connected to an output terminal, or a short-circuit status in which the output terminal is connected to ground, and a driving device including the same.
2. Description of the Related Art
Abnormal connection detecting circuits are used for responding to abnormalities, such as an open status and a short-circuit status. An open status is when a load is not connected to an output terminal through which power is supplied to the load. A short-circuit status is when the output terminal is connected to ground. When these abnormalities occur, the abnormal connection detecting circuit stops power from being supplied to the load, or displays a warning about the abnormality.
FIG. 7 is a circuit diagram of an example of a conventional abnormal connection detecting circuit (see, for example, Patent Document 1).
In FIG. 7, a high-level signal is input to an AND circuit 126 via a driving signal input terminal 127, and a drain voltage Vd of an NMOS transistor 114 is greater than or equal to a reference voltage V1. In this case, an output terminal of the AND circuit 126 becomes high-level, and a gate voltage Vg of the NMOS transistor 114 increases, so that the NMOS transistor 114 is switched on, and an electrical current is supplied to a load 112.
When the drain voltage Vd of the NMOS transistor 114 is less than the reference voltage V1, the output terminal of the AND circuit 126 becomes low-level, and the gate voltage Vg of the NMOS transistor 114 decreases, so that the NMOS transistor 114 is switched off, and electric supply to the load 112 is stopped. When a power line of the load 112 is disconnected, the drain voltage Vd of the NMOS transistor 114 becomes substantially 0 V, and therefore, the gate voltage Vg continues to decrease. When a signal input to the driving signal input terminal 127 is high-level, and the gate voltage Vg of the NMOS transistor 114 is less than or equal to a reference voltage V2, a comparator 132 outputs a high-level signal, so that an output terminal of an AND circuit 134 becomes high-level. Accordingly, a predetermined abnormality output signal indicating an abnormal status is output.
Patent Document 1: Japanese Laid-Open Patent Application No. 2004-86257
However, the drain voltage Vd is an extremely low voltage when the NMOS transistor 114 is switched on. Therefore, in the method of comparing the drain voltage Vd and the reference voltage V1, a comparison is made between microscopic voltages of near 0 V, which requires a high-precision comparator. Further, it is difficult to configure a comparator for detecting voltages of near 0 V with a single power source, which leads to high costs. Moreover, when a load current is low, or when a transistor with a low saturation voltage is used, the drain voltage Vd decreases even further, which makes it difficult to detect abnormalities with high precision.